In digital signal processing, generally, the greater the number of bits to be digitized, the higher becomes the gradation. However, as the number of bits increases, the circuit scale and the number of pins of device are increased. Various methods have been proposed so far for curtailing the number of bits while maintaining the gradation in digital signal processing, an example of which is disclosed in Japanese Laid-open Patent No. 2000-224047.
As a more general circuit, a bit number curtailing circuit using adder and delay unit for noise shaping is used widely. This prior art is explained in FIG. 5, FIG. 6, and FIG. 7 as a conventional example.
FIG. 5 is a block diagram showing a structure of the conventional example. In the diagram, a picture quality correction circuit 500 applies various digital signal processings on m bits (m being an integer) of input signal supplied through an input terminal 520. At this time, bits are processed depending on the signal processing content so that the bit precision of the input signal composed of m bits may not be spoiled. Consequently, a noise shaping circuit 510 composed of an adder 511 and a delay unit 512 curtails the number of bits, and converts the signal composed of m bits into a signal composed of n bits (n being an integer and smaller than m).
FIG. 6 shows this mode. In FIG. 6, m in FIG. 5 is 10, and n is 8. Value 600 shows the output of the picture quality correction circuit 500, and the output of the picture quality correction circuit 500 is assumed to be 30F in hexadecimal notation. That is, 30F in hexadecimal notation is 783 in decimal notation.
When converted to 8 bits, it is 195.75, and by discarding simply, it is 195. As a result, the portion below the decimal point, that is, the portion of two lower bits of 10 bits is ignored. The noise shaping circuit 510 modulates the portion of two lost bits by PWM (pulse width modulation), and adds to the higher bits, so that the information of the lower bits can be reproduced artificially by the integrating effect.
The adder 511 adds the two lower bits of the output of the delay unit 512 and the output of the picture quality correction circuit 500 of m bits, and supplies the sum into the delay unit 512. By the output of eight higher bits excluding two lower bits of the output of the delay unit 512, PWM processing of lower bits is realized. Herein, since the adder 512 generally overflows, a limiter is provided in a rear stage.
Value 601 shows the timing chart of value after conversion of the number of bits to eight bits by the noise shaping circuit 510. Value 602 is a timing chart of value in a scanning period next to 601, 603 in a scanning period next to 602, and 604 in a scanning period next to 603. In ten bits, the signal of 30F is converted into C3, C4, C4, C4, C3, C4, C4, C4, . . . C3 is 195 in decimal notation, and C4 is 196. Integrating C3, C4, C4, C4, the result is 195.75, and it is known that the precision of ten bits is reproduced artificially.
FIG. 7 shows a mode of image displayed on the screen after the processing above. In FIG. 7, scanning line 702 is a scanning line next to scanning line 701, scanning line 703 is a scanning line next to scanning line 702, and scanning line 704 is a scanning line next to scanning line 703. Value 601 is value displayed in scanning line 701, 602 in scanning line 702, 603 in scanning line 703, and 604 in scanning line 704. Solid cell indicates pixel of C3 and blank cell indicates pixel of C4. Therefore, pixels slightly different in luminance coexist. The coexistent pattern does not change so much, and may be sometimes close to stationary state.
In this process, when the input signal is steady luminance, in particular, in the case of liquid crystal panel of large size and low resolution, for example, in a 20 V type with resolution VGA of 640×480 dots, that is, one pixel is large in size, the PWM component may be visually recognized as beat noise or vertical line noise.
Generally, a video signal changes every moment, and the PWM component is not so obvious. On the other hand, when the input signal is no input, it is a signal of 0 in terms of DC. That is, 0 in terms of DC means black, and usually it is not obvious if there is noise, but in the event of offset of video signal by the picture quality correction circuit 500 (corresponding to user's adjustment for raising the black level), PWM component can be visually recognized as noise.